In the world of computers and processors there is an unrelenting drive for additional computing power and faster calculation times. In this context, then, systems in which several processors can be combined to work in parallel with one another are necessary.
Imaging systems which obtain visual images and perform various manipulations with respect to the data and then control the display of the imaged and stored data inherently require large amounts of computations and memory. Such imaging systems are prime candidates for multi-processing where different processors perform different tasks concurrently in parallel. These processors can be working together in the single instruction, multiple data mode (SIMD) where all of the processors are operating from the same instruction stream but obtaining data from various sources. Or the processors can be working together in the multiple instruction, multiple data mode (MIMD) where each processor is working from a different set of instructions and working on data from different sources. For different operations, different configurations are necessary.
When several of the parallel processors are working on a common task there is usually the need to communicate between processors. In some situations the processors can achieve this communication by passing messages one to another. In other situations semaphore signals must be passed for control purposes. However, there are situations where cycle by cycle synchronization is necessary and in these situations it is time consuming to pass messages and to rely on semaphore signaling.
To compound the problem even further, the various individual processors may be working in conjunction with a first set of processors at one period of time and with a different set of processors at a different time. Any system then that establishes synchronized control must do so in a flexible quickly changing manner.
In situations where several processors are synchronized the implication is that they will all execute their instructions, which can be different for each processor, in lock step with each other. However, since the instructions for each processor may require more or less time to execute, or may be subject to unanticipated interrupts (such as, for example, a faulty memory transfer) some mechanism must be in place to pace the processors if synchronism is to be maintained under all conditions.
There is thus a need in the art for a system which handles multi-processors such that any of the processors can be synchronized with any one or more other processors for a variable amount of time all without interchanging messages or semaphore signals and regardless of the execution time of any one or more instructions.
One method of solving the huge interconnection problem in complex systems, such as the image processing system shown in one embodiment of the invention, is to construct the entire processor as a single device. Conceptually this might appear easy to achieve, but in realty the problems are complicated.
First of all, an architecture must be created which allows for the efficient movement of information while at the same time conserving precious silicon chip space. The architecture must allow a very high degree of flexibility since once fabricated, it can not easily be modified for different applications. Also, since the processing capability of the system will be high there is a need for high bandwidth in the movement of information on and off the chip. This is so since the physical number of leads which can attach to any one chip is limited.
It is also desirable to design an entire parallel processor system, such as an image processor, on a single silicon chip while maintaining the system flexible enough to satisfy wide ranging and constantly changing operational criteria.
It is further desirable to construct such a single chip parallel processor system whether the processor memory interface is easily adaptable to operation in various modes, such as SIMD and MIMD, as well as adaptable to efficient on-off chip data communications.